IPC CID — Certified Interconnect Designer — Study Guide

IPC CID — Certified Interconnect Designer — Study Guide

Credential: IPC CID (Certified Interconnect Designer) Issuing body: IPC (Association Connecting Electronics Industries) Jurisdiction: International (US-based body; worldwide adoption) Level: Professional — the basic designer credential in the IPC family (CID+ is the advanced tier) Prerequisites: None formal per IPC; in practice, working knowledge of PCB design and IPC-2221/2222. The basic endorsement requires a 110-question exam (73% pass per training providers). CID certifications are valid for life (per IPC training providers; not confirmed on ipc.org's product page — verify before relying). Renewal: None — valid for life.

CID is the design-side credential: it certifies you can design a manufacturable, reliable PCB. Its siblings certify other roles: CIS (A-610/J-STD-001) certifies assembly acceptance (covered in the merged CIS guide in this folder), CIT certifies trainers, and CID+ certifies advanced designers. Don't confuse them — the exam, the audience, and the body of knowledge differ.

1. Pathway — how it's earned

1. Build working PCB design knowledge. CID assumes you already lay out boards. Candidates typically come from 1–3 years of CAD layout work (Altium, KiCad, Allegro, PADS) or adjacent EDA roles.
2. Study the IPC design standards family. The exam is standards-referenced: IPC-2221 (generic PCB design), IPC-2222 (rigid organic), IPC-2223 (flex), IPC-7351 (land patterns), IPC-6012 (rigid board qualification), IPC-A-600 (board acceptability awareness), IPC-4101 (laminate materials), IPC-2221B Section 6 (electrical considerations). You don't memorize these — you learn what each governs so you can reason from them.
3. Take a CID preparation course (typical: 3 days). Training providers run the standard CID curriculum ending in the exam.
4. Sit the 110-question exam. Pass mark 73% per training providers. The exam is multiple-choice, standards-application oriented — it tests whether you can make correct design decisions, not recite clauses.
5. Hold for life. No renewal cycle (per current provider reporting).

Exam format note: the 110-question / 73% figures come from IPC training providers, and the IPC CIS Policies & Procedures v7.2 document confirms the basic-endorsement exam structure family. Exact current delivery details should be confirmed with IPC or your training provider before scheduling — IPC periodically revises the program.

2. Knowledge domains

Domain A — Design process and documentation (why CID exists)

A PCB design is a contract between design intent and manufacturing reality. CID tests the full flow: schematic capture discipline (net naming, DRC-clean schematics), component selection for manufacturability (package availability, second sources), stackup definition, placement, routing, plane strategy, DFM review, and fabrication/assembly documentation packages (Gerbers/ODB++/IPC-2581, fab drawings, assembly drawings, BOM discipline).

Theory: why documentation discipline matters. Every ambiguity in the fab package becomes a question to the CAM engineer, a delay, or a misbuilt board. CID treats the drawing package as an engineering deliverable with the same rigor as the layout: title blocks, revision control, material callouts (IPC-4101 slash sheets), finish specifications (ENIG, HASL, OSP with their tradeoffs), and solder mask/silkscreen requirements. Know what belongs on a fab drawing vs. what belongs in the Gerbers.

Domain B — Materials and stackup (IPC-4101, IPC-2221)

Theory: the stackup is an electrical and mechanical design, not just "layers." Prepreg vs. core (core = cured laminate with copper both sides, fixed thickness; prepreg = uncured glass/resin that bonds cores and flows during lamination). Dielectric constant (Dk) and dissipation factor (Df) of the laminate set impedance and loss: FR-4 Dk ≈ 4.2–4.6 (frequency- and resin-content-dependent — never treat it as exactly 4.4 in a calculation you defend), Df ≈ 0.02. High-speed designs move to low-loss laminates (Dk ≈ 3.0–3.5, Df ≈ 0.002–0.008) because dielectric loss scales with frequency.

Copper weight: 1 oz copper = 1.37 mils (35 µm) thick. Plane layers are often 1 oz; outer layers 1 oz finished (starts 0.5 oz + plating). Heavier copper (2 oz+) for power — but heavy copper etches with more undercut, widening tolerance on fine features. CID expects you to know these tradeoffs, not just the numbers.

Symmetry rule: stackups must be balanced about the center (copper distribution and dielectric thickness) or the board warps during reflow — asymmetric copper (e.g., solid plane on L2, sparse routing on L5 of a 6-layer) is the classic warpage cause. The exam loves warpage root-cause questions.

Glass styles and resin content affect Dk and CTE; Tg (glass transition temperature) must exceed your assembly thermal exposure — lead-free reflow peaks ~245–260°C, so standard Tg 130–140°C FR-4 is marginal for lead-free; Tg 150–170°C is the safe choice. CTE mismatch (copper ~17 ppm/°C in-plane, FR-4 ~12–16 in-plane but ~50–70 through-thickness below Tg) drives via/barrel fatigue — this is why high-Tg and low-CTE materials exist.

Domain C — Electrical design: impedance, crosstalk, power integrity

Controlled impedance — derivation: a PCB trace over a reference plane is a transmission line. Microstrip characteristic impedance Z0 ≈ (87 / √(Dk + 1.41)) × ln(5.98H / (0.8W + T)), where H = dielectric height, W = trace width, T = copper thickness (all same units). The physics: Z0 = √(L/C) per unit length; narrower traces or greater height raise L and lower C, raising Z0. CID doesn't require the formula from memory, but requires the directional knowledge: to lower Z0, widen the trace or thin the dielectric; Dk tolerance (±10% on FR-4) is why fab shops adjust trace width at CAM time.

Why impedance control matters: when trace length exceeds ~1/10 of the signal rise-time length (length where propagation delay ≈ rise time/10), reflections from impedance discontinuities cause ringing and eye closure. Rule: treat as transmission line when delay > tr/6 (conservative) — for 1 ns rise time in FR-4 (delay ≈ 6 in/ns... actually ~150 ps/in, so 1 ns ≈ 6.7 in), traces longer than ~1 inch need impedance control. This is the quantitative reasoning CID tests.

Crosstalk: capacitive + inductive coupling between parallel traces. Mitigation hierarchy: increase spacing (3W rule — spacing ≥ 3× trace width drops crosstalk to ~tolerable for most digital), route over continuous reference plane (return current follows the trace; a plane split forces the return around the gap, creating a loop antenna — never route high-speed signals across plane splits), keep parallel run lengths short, use guard traces only as a last resort (they must be stitched to ground frequently or they resonate).

Power integrity: the PDN (power distribution network) must present low impedance from DC to the signal bandwidth. Target impedance: Z_target = (V_dd × ripple%) / I_transient. Decoupling strategy: bulk capacitors (10–100 µF) for low frequency, mid-range (1–10 µF), and small (0.1 µF, 0.01 µF) for high frequency — placed to minimize loop inductance (close to the load, vias directly to planes). Plane capacitance (closely spaced power/ground planes) handles the highest frequencies where discrete caps go inductive. Know the self-resonant frequency concept: above SRF a capacitor is an inductor — more capacitance is not always better.

Domain D — Thermal and mechanical design

Thermal: copper planes are the primary heat spreaders in most boards (thermal conductivity of copper ≈ 400 W/m·K vs. FR-4 ≈ 0.3). Thermal vias under hot components conduct heat to inner planes or the opposite side. Derating: components' power ratings assume specific thermal environments — CID expects awareness that layout is thermal design.

Mechanical: board thickness (0.062 in / 1.6 mm standard; thinner for dense HDI, thicker for stiffness), mounting-hole keepouts, connector mechanical stress (through-hole connectors need anchoring consideration), depanelization method (V-score, tab-route, laser) and its keepout requirements, component placement relative to board edges for wave/selective soldering.

CTE and reliability: the through-thickness CTE of FR-4 (~50–70 ppm/°C) vs. copper barrel (~17) is why thick boards with small vias fail barrel fatigue in thermal cycling — aspect ratio (board thickness : drilled hole diameter) limits exist for this reason (typically ≤ 10:1 for standard processes; HDI uses stacked vias to beat it).

Domain E — DFM/DFA and land patterns (IPC-7351, IPC-2222)

Land patterns (IPC-7351): three density levels — Level A (maximum/protrusion, for hand-solderable and low-density), Level B (median/nominal — the default), Level C (minimum, high-density). CID tests that you select the density level deliberately based on assembly process and density, and that courtyard/excess calculations drive component spacing.

DFM rules you must be able to apply: annular ring minimums (external ≥ 0.002 in / 0.05 mm per IPC-6012 Class 2; know Class 1/2/3 exist and what changes), solder mask dams between fine-pitch pads, via-in-pad rules (filled/capped for BGA, tented acceptable for low-reliability), trace-to-edge clearances, copper-to-board-edge for routing vs. scoring, teardropping at trace-to-pad junctions for etch robustness.

DFA rules: component orientation consistency (polarity marking), tombstoning risk (small chip components: symmetric land patterns, avoid one pad tied to a large plane without thermal relief), wave-solder shadowing (orientation relative to wave direction), keepouts under RF shields and tall components, test-point access (bed-of-nails needs 0.100-in grid access or flying-probe allowance).

Why thermal relief matters: a pad directly connected to a large copper plane sinks heat during soldering — the joint on the plane side won't wet properly (cold/solder-starved joint). Thermal relief spokes limit heat conduction while maintaining electrical connection. But for high-current paths, thermal reliefs add resistance and heating — the exam tests this tradeoff.

Domain F — High-density and special technologies (awareness level)

HDI (microvias: ≤ 0.006 in / 0.15 mm, typically laser-drilled; stacked vs. staggered via structures), flex/rigid-flex (IPC-2223: bend radius rules — minimum bend radius ≈ 6× thickness for single-layer flex, more for multilayer; avoid vias/plated holes in bend areas; teardrop at rigid-flex transitions), embedded components (awareness), controlled-depth drilling (back-drilling for stub removal in high-speed — why: via stubs resonate at frequencies where stub length ≈ λ/4).

Domain G — Standards literacy (the CID meta-skill)

Know what each standard governs (you will be tested on selecting the right standard, not reciting clauses):

• IPC-2221: generic design rules (the parent).
• IPC-2222: rigid organic boards (the workhorse).
• IPC-2223: flexible/rigid-flex.
• IPC-7351: land pattern geometry.
• IPC-6012: rigid board qualification and performance (what the fab must deliver; Classes 1/2/3).
• IPC-A-600: board acceptability (what the inspector sees; target/acceptable/nonconforming).
• IPC-4101: laminate material specification (slash sheets).
• IPC-2221B §6: electrical clearance/spacing vs. voltage (the spacing tables — know they exist and scale with voltage, coating, and altitude).

3. Key equations (units + assumptions)

4. Worked examples

Example 1 — Impedance control decision. A 4-layer board (signal–GND–power–signal), 0.062-in thick, dielectric H = 0.008 in between L1 and L2, FR-4 Dk = 4.3, 1 oz copper (T = 1.4 mils). What trace width gives 50 Ω single-ended? Using the microstrip approximation: try W = 14 mils. 87/√(4.3+1.41) = 87/2.39 = 36.4. ln(5.98×8/(0.8×14+1.4)) = ln(47.84/12.6) = ln(3.80) = 1.335. Z0 ≈ 36.4 × 1.335 ≈ 48.6 Ω. W = 13 mils → ln(47.84/11.8) = ln(4.05) = 1.399 → Z0 ≈ 50.9 Ω. Answer: ~13–14 mils → specify 50 Ω controlled, let the fab tune ±10%. CID lesson: you calculate the nominal, then specify impedance control and let CAM adjust for their Dk — never hard-specify width to 3 decimals.

Example 2 — Transmission-line threshold. A microcontroller drives a 2-ns rise-time clock across 4 inches of FR-4 (delay ≈ 160 ps/in → 640 ps total). tr/6 = 333 ps < 640 ps → treat as a transmission line: route with controlled impedance, terminate the source (series R ≈ Z0 − Z_driver), keep stubs short. A 0.5-ns rise-time signal on the same 4-in trace (tr/6 = 83 ps) is deep into transmission-line territory — series termination is mandatory, not optional.

Example 3 — Stackup symmetry. A 6-layer design: L1 signal, L2 GND plane, L3 signal, L4 signal, L5 power plane, L6 signal, with cores/prepreg arranged so L2–L3 and L4–L5 dielectrics match. Copper balance: L2 is a full plane, L5 is a full plane — symmetric. But L1 is densely routed while L6 is sparse — during reflow, asymmetric resin/copper distribution across the centerline causes bow. Fix: add copper thieving (hatched fill) on sparse layers, or mirror the routing density. CID tests this as a warpage root-cause question.

Example 4 — Decoupling target. A 1.0-V core rail allows 5% ripple (50 mV) with a 5-A transient step. Z_target = 0.050 / 5 = 10 mΩ from DC to ~100 MHz. A single 0.1-µF ceramic (SRF ~15 MHz in 0402) can't do this alone — you need a capacitor network (bulk 47 µF + several 1–10 µF + many 0.1 µF) plus closely spaced power/ground planes, with vias minimizing mounting inductance. The exam tests the concept that PDN design is a system, not a capacitor count.

Example 5 — Land pattern density selection. A 0.5-mm-pitch QFN on a board assembled with reflow only, moderate density. IPC-7351 Level B (nominal) is the default — Level C would risk bridging at this pitch without proven process control; Level A wastes routing space. Answer: Level B, with solder-mask-defined pads considered for the fine pitch, and thermal vias in the exposed pad filled/capped (not open — open vias wick solder away from the thermal pad joint).

5. Standards cross-reference (what CID tests from each)

6. Pitfalls & exam strategy

Pitfalls:

1. Memorizing clauses instead of learning tradeoffs. The exam asks "which is better and why" — clause recitation fails these.
2. Forgetting the fab is a partner. Questions about "who adjusts trace width for impedance" — the CAM engineer does, from your controlled-impedance specification.
3. Via-in-pad without fill. Open vias in BGA/QFN thermal pads wick solder — always specify filled/capped (IPC-4761 Type VII).
4. Plane splits under high-speed routing. The #1 signal-integrity layout error; the exam will show you a stackup and ask what's wrong.
5. Density-level mismatch. Level C land patterns with a Level A assembly process = bridging defects.
6. Ignoring aspect ratio. 0.062-in board with 0.008-in vias = 7.75:1, fine. 0.093-in board with 0.006-in laser vias assumed drillable — not manufacturable in standard process.

Exam strategy: 110 questions, generous time — pace at ~1.5 min/question with buffer. The exam rewards design judgment: when torn between two answers, pick the one that favors manufacturability and reliability over density or cost. Flag standards-lookup questions and answer judgment questions first. 73% pass means you can miss ~30 — don't burn 10 minutes on one stackup calculation.

7. Practice problems (answers at end)

1. A 6-layer board warps after lead-free reflow. The stackup is symmetric in dielectric thickness but L2 (GND plane) is solid copper while L5 (power) is 80% etched away. What is the most likely cause, and the fix?
2. For a 50-Ω microstrip on Dk = 4.0, H = 10 mils, 1-oz copper: should the trace be wider or narrower than the 13–14 mils computed for Dk = 4.3, H = 8 mils? Explain without calculating.
3. A 3.3-V rail allows 3% ripple with a 3-A transient. Compute Z_target. A junior proposes a single 10-µF capacitor at the regulator output. Why is this insufficient?
4. Which IPC-7351 density level do you choose for a 0.4-mm-pitch BGA on a high-density smartphone-class board, and why?
5. A designer routes a 480-Mbps USB differential pair across a split in the ground plane. Name two specific signal-integrity consequences.
6. True/false: "CID certification expires after 3 years and requires re-examination." Justify from the program facts in this guide.

Answers:

1. Cause: asymmetric copper distribution about the centerline — solid plane vs. etched plane creates asymmetric CTE/resin stress during reflow. Fix: copper thieving/balancing on L5 (or redistribute plane copper symmetrically), and verify balance in the fab's CAM review.
2. Wider. Lower Dk raises Z0 (less capacitance), and greater H raises Z0 — both effects must be compensated by widening the trace (more capacitance to the plane) to hold 50 Ω.
3. Z_target = (3.3 × 0.03)/3 = 33 mΩ. A single 10-µF cap has mounting inductance (~1–2 nH) making it inductive above a few MHz, and one capacitor can't cover DC-to-100-MHz — a PDN needs a capacitor network plus plane capacitance.
4. Level C (minimum). At 0.4-mm pitch, Level A/B lands would bridge or consume unroutable space; Level C is designed for high-density assembly with proven process control.
5. (1) The return current must detour around the split, enlarging the loop area → increased EMI and crosstalk; (2) the impedance discontinuity at the split causes reflections → eye closure/bit errors. (Also acceptable: increased radiated emissions making EMC failure likely.)
6. False. Per IPC training-provider reporting, CID is valid for life with no renewal — unlike the CIS credentials, which renew every 24 months.

Original ETS reference writing, verified against public sources on 2026-09-30. Thin sourcing is flagged inline. Not legal advice — confirm current editions with the issuing body.