Electronics/Embedded — Good-to-Know Rules of Thumb & Veteran Knowledge
Standard-practice and niche credentials, standards mastery, order-of-magnitude reflexes, and the things exams don't test. For working electronics and embedded engineers.
1. Standard-practice and niche credentials — what each is, who needs it, when to pursue it
IPC CID+ — Advanced Certified Interconnect Designer. The step above CID: high-speed design, HDI, advanced SI/PI, complex stackups. Pursue after 3–5 years of design experience (training providers recommend this) when your boards carry DDR, PCIe, 10G+ SerDes, or dense HDI. CID gets you hired as a layout engineer; CID+ marks you as the signal-integrity-capable designer.
IPC-A-610 CIT / J-STD-001 CIT (Certified IPC Trainer). The trainer tier above CIS — you become the person who certifies CIS holders at your company. Pursue when you're the senior manufacturing/quality engineer and your site needs in-house certification capacity (cheaper and faster than sending everyone to a training center). Requires deeper standard knowledge than CIS plus instructional ability.
IPC-A-600 CIS endorsement / IPC-6012 CIS endorsement. Inspector endorsements for bare-board acceptability (A-600) and rigid-board qualification (6012). Pursue if you're in incoming inspection, supplier quality, or fab liaison — they certify you can judge a bare board, distinct from the A-610 assembly judgment.
Certified Electronics Technician (CET / CETa). The generalist electronics technician credential (ETA International). Standard-practice for bench technicians, field service, and repair. Pursue early-career if your work is hands-on troubleshooting rather than design — it's the technician's counterpart to the engineer's degree.
FCC GROL (General Radiotelephone Operator License). Covered by a full guide in the Telecom/RF folder. Electronics engineers meet it when their work touches transmitters — avionics, marine, radar. If your embedded product has a radio and you do hands-on TX work, know what it is.
PE Electrical and Computer: Electronics (niche). There is an NCEES PE exam path for electronics engineers, but the industrial exemption covers most industry design work — PE matters mainly for consulting, stamping, or public-sector roles. Pursue if your career moves toward independent practice.
ARM Accredited Engineer (AAE) / Accredited MCU Engineer (AAME). Vendor-ecosystem credentials for ARM-based embedded work. Niche — pursue only if your employer or client base standardizes on ARM and values the badge; the underlying knowledge (Cortex-M architecture, CMSIS, low-power design) is what actually matters.
IEEE WCET (Wireless Communication Engineering Technologies). The IEEE ComSoc wireless credential. Niche but legitimate for RF/wireless engineers who want an IEEE-backed badge. Pursue if wireless is your specialty and you want portable proof of it.
2. Standards & regulations mastery
IPC-A-610 — Acceptability of Electronic Assemblies
Know cold: the Target/Acceptable/Nonconforming/Process-Indicator taxonomy; Class 1/2/3 and how class changes every criterion; through-hole fill minima (75% Class 2/3); SMT overhang/voiding rules; the solder-anomaly vocabulary (bridging, dewetting, disturbed, icicles).
How compliance is demonstrated: inspection to the standard's criteria — visual, x-ray for BGA/QFN, documented accept/reject with class identified.
Common violations: class blindness (judging Class 3 to Class 2 criteria); scrapping process indicators; lead-free joints misjudged as cold.
IPC-2221 / IPC-2222 — PCB design standards
Know cold: 2221 as the generic parent (§6 spacing vs. voltage); 2222 rigid specifics (annular ring, conductor sizing). These are the design rules behind the CID exam.
Common violations: annular ring below class minimum on dense designs; trace spacing at high voltage without consulting §6; via aspect ratios beyond process capability.
IPC-6012 — Rigid board qualification
Know cold: Classes 1/2/3 (Class 2 = default commercial); what qualification means — the fab is tested against performance requirements (thermal stress, plating thickness, dielectric). This is the document you cite when a fab lot fails.
Common violations: assuming Class 3 without specifying it on the fab drawing (you get Class 2); not requiringIST/thermal-stress coupons on high-reliability builds.
IPC-A-600 — Board acceptability
Know cold: the bare-board defect vocabulary — measling, crazing, delamination, lifted lands, plating voids, etch defects. Know which are acceptable within limits vs. always rejectable.
Common violations: confusing board defects (supplier quality, A-600) with assembly defects (A-610) in failure analysis — misassigning root cause.
IEC 61010-1 — Measurement/control/lab equipment safety
Know cold: measurement categories (CAT II/III/IV) and what they mean — transient overvoltage environment. Your multimeter's CAT rating must meet or exceed the circuit's category. Pollution degrees, clearance/creepage for mains circuits.
Common violations: using a CAT II meter on a CAT III distribution panel — arc-flash and transient risk; the #1 lab-safety error.
IEC 62368-1 — AV/ICT equipment safety (hazard-based)
Know cold: the hazard-based philosophy — identify energy sources (electrical, thermal, mechanical), classify them (Class 1/2/3), apply safeguards. Replaced 60950/60065. Relevant when your product is ICT/AV and needs CB-scheme certification.
Common violations: designing to the old prescriptive standards' checklists instead of the hazard-based analysis; missing safeguard requirements for accessible hazardous voltages.
UL 508A — Industrial Control Panels
Know cold: SCCR marking, component selection within the panel's short-circuit rating, wire sizing and separation, listing implications of field modification. (Also covered in the Electrical/Power folder.)
Common violations: panel SCCR below available fault current; mixing non-listed components into a listed panel.
CISPR 32 / CISPR 35 — EMC emission/immunity for multimedia
Know cold: 32 = emissions (radiated/conducted limits, Class A industrial vs. Class B residential — Class B is ~10 dB stricter); 35 = immunity (ESD, EFT, surge, radiated RF, conducted RF test levels and performance criteria A/B/C). Know that layout and filtering decide pass/fail long before the lab.
How compliance is demonstrated: accredited-lab testing to the standards, test reports in the technical file.
Common violations: designing without pre-compliance testing, then failing at the accredited lab ($$$); assuming a modular radio approval covers the host product's unintentional emissions (it doesn't — the host still needs Part 15B/CISPR 32 evaluation).
MIL-STD-810H — Environmental test methods
Know cold: it's a tailorable method set (vibration, shock, temp, humidity, altitude, sand/dust...), not a pass/fail spec — you select and tailor methods to the life-cycle environment. "Designed to MIL-STD-810" without cited methods/severities is marketing, not engineering.
Common violations: citing 810 without tailoring; testing to lab conditions that don't match the deployment environment.
DO-254 — Airborne electronic hardware design assurance
Know cold: the DAL (Design Assurance Level) framework A–E, requirements traceability, verification independence, configuration management. It's a process standard — it doesn't tell you the circuit works, it requires evidence that you verified it works at the rigor matching the failure consequence.
Common violations: treating DO-254 as a testing standard rather than a lifecycle-assurance standard; requirements written after the design (traceability theater).
FCC Part 15 — Radio Frequency Devices
Know cold: Subpart B = unintentional radiators (your digital product's emissions — Class A/B limits); Subpart C = intentional radiators (your radio — with modular approval paths). Supplier's Declaration of Conformity (SDoC) vs. Certification (telecom certification body) authorization paths.
How compliance is demonstrated: accredited-lab test reports, proper labeling (FCC ID or SDoC statement), records retained.
Common violations: no Part 15B evaluation because "we have a pre-certified module" — the host's digital circuitry still radiates; modifying a certified module's antenna/layout voids the grant.
EU EMC Directive / Radio Equipment Directive (RED) / RoHS / REACH
Know cold: EMC Directive (2014/30/EU) — CE marking via harmonized standards (EN 55032/55035); RED (2014/53/EU) — radio equipment, adds spectrum efficiency and (increasingly) cybersecurity requirements; RoHS (2011/65/EU + 2015/863) — 10 restricted substances, homogeneous-material thresholds (0.1% / 0.01% for cadmium); REACH (EC 1907/2006) — SVHC disclosure above 0.1% w/w, SCIP database notification.
How compliance is demonstrated: technical documentation, EU Declaration of Conformity, CE mark, authorized representative/importer obligations.
Common violations: RoHS non-compliance from a single component's exemption expiring; REACH SVHC list updates ignored (the candidate list grows twice yearly); assuming FCC test data transfers to CE (different limits, different standards).
ITAR / EAR export controls
Know cold: ITAR (22 CFR 120–130) = defense articles on the USML — strict, no commercial balancing; EAR (15 CFR 730–774) = dual-use items on the CCL — ECCN classification, license exceptions. Deemed exports: sharing controlled technical data with a foreign national inside the US is an export.
Common violations: emailing design files to an overseas contractor without jurisdiction/classification review; assuming "commercial" means uncontrolled.
3. Rules of thumb
Order-of-magnitude numbers:
- FR-4: Dk ≈ 4.2–4.6, Df ≈ 0.02, delay ≈ 150–180 ps/in. 1 oz Cu = 1.37 mils.
- Decoupling: 0.1 µF per power pin is folklore — do the Z_target math; at 100+ MHz you need plane capacitance, not more discretes.
- Thermal: still air θ_ja for a QFN ≈ 30–40°C/W; with thermal vias + planes ≈ 20–25. A 2-W part in still air without thermal design runs ~60–80°C above ambient — do the multiplication before the layout.
- ESD: HBM 2 kV kills most unprotected gates; CDM failures happen below 500 V on fine-geometry parts. If you handle boards without a strap, you are the test lab.
- Soldering: lead-free reflow peak 245–260°C; hand-iron 350–370°C tip, 2–4 s dwell max per joint.
Sanity checks:
- If your PDN has one capacitor value, it's wrong.
- If your stackup isn't symmetric, it will warp — physics doesn't negotiate.
- If the schematic DRC is dirty, the layout inherits the dirt. Clean schematics are free; clean layouts are expensive.
- A 50-Ω trace that's 40 Ω at the fab means the fab tuned for their Dk — check the impedance coupon report, don't panic.
Unit-conversion reflexes:
- mils ↔ mm: 1 mil = 0.0254 mm (40 mils ≈ 1 mm). Think in mils for fab, mm for mechanical.
- dB: 20 dB = 10× voltage, 10 dB = 10× power. EMC limits in dBµV — 6 dB over the limit is 2× the voltage, not "a little over."
- °C/W × watts = temperature rise. Always.
Typical safety factors:
- Voltage ratings: capacitors at ≤70% of rated voltage for reliability (derating); 50% for high-reliability.
- Current: traces and vias at ≤50% of IPC-2221 current-carrying estimates for thermally constrained designs.
- Timing: 20–30% timing margin on setup/hold after SI simulation — models lie a little.
4. Veteran knowledge
Costly beginner mistakes:
- Layout before stackup. Routing on an undefined stackup, then discovering impedance is unachievable. Define the stackup first — it's the foundation everything electrical stands on.
- Autorouter trust. The autorouter doesn't understand return currents, plane splits, or crosstalk. Veterans hand-route critical nets and let the machine do the rest — or route everything by hand on high-speed boards.
- No pre-compliance EMC testing. First EMC test at the accredited lab is a $5,000–$15,000 lesson. A $500 near-field probe and a spectrum analyzer in your lab find 80% of problems for 5% of the cost.
- Ignoring the fab's capabilities. Designing 3-mil trace/space when your fab's standard process is 5/5 — every tolerance you push costs yield. Call the fab before layout, get their capabilities document, design inside it.
- Test-point starvation. No test points = no debugging = board spins for avoidable reasons. Bed-of-nails or flying-probe access is a design requirement, not a luxury.
- Firmware as an afterthought. The embedded engineer who gets the board last discovers the missing pull-ups, the unroutable debug header, the reset circuit that doesn't. Hardware/software co-design reviews catch these when they're free.
When to call a specialist:
- SI/PI simulation on multi-gigabit SerDes — the tools and judgment take years; hire the consultant for the first one and learn from their models.
- EMC failures that survive two board spins — the near-field expert sees in an hour what you'll find in a month.
- Functional safety (IEC 61508/UL 1998) for safety-critical embedded — the process rigor is a specialty; don't freelance it.
- RF matching and antenna design above a few GHz — Smith-chart intuition at microwave frequencies is its own discipline.
What exams don't test: supplier relationships (your best DFM reviewer is a fab CAM engineer who likes you), the judgment to respin vs. rework, cost engineering (a $0.02 component choice × 1M units), and the reality that most field failures are connectors, solder joints, and firmware — in that order.
5. Bring-up, debug, and bench quick-reference
The bring-up ritual (order matters): (1) visual inspection — solder bridges, reversed polarity parts, missing components; (2) resistance check — power rails to ground before applying power (a short reads as near-zero ohms); (3) current-limited power-up — set the supply limit to ~2× expected draw and watch; (4) rail voltages — every rail, at the load, under the current limit; (5) clock — the oscillator runs before anything else debugs; (6) reset — asserted then released cleanly; (7) communication — JTAG/SWD connects before firmware blames. Ninety percent of "dead board" failures are found in steps 1–4.
Oscilloscope discipline: probe ground lead inductance rings on fast edges — use the spring ground tip for anything above ~50 MHz, or you're measuring your probe, not your signal. Bandwidth rule: scope ≥ 5× the signal bandwidth for analog fidelity, ≥ 3× for digital timing. The veteran's first question on any weird waveform: "is this the circuit or the measurement?"
Decoupling quick rules: one 100 nF ceramic per power pin, placed closest to the pin with minimal loop; bulk capacitance (10–47 µF) per rail region; ferrite bead + capacitor pi-filters for noise-sensitive analog rails (but check the bead's DC bias derating — a "600 Ω" bead at full current may be 100 Ω). Power-plane capacitance handles the mid-frequencies; know the three-tier model (bulk, ceramic, plane).
Common failure signatures: rail shorted at power-up → solder bridge or reversed tantalum (they fail short, dramatically); MCU runs but peripherals flaky → clock or reset integrity; intermittent failures with temperature → cold solder joint or marginal timing; works on the bench, fails in the enclosure → grounding/shielding or thermal; fails only at high load → PDN impedance or thermal throttling.
ESD handling that actually matters: wrist straps and grounded mats at the bench (the exam answer), but the field answer is that unprotected handling during assembly is the dominant ESD damage vector — design protection (TVS diodes, series resistors on exposed lines) because you cannot control every handler. HBM 2 kV is the "walks across carpet" baseline; IEC 61000-4-2 contact 8 kV is the product-survival bar.
Firmware-debug leverage: instrument first — a spare UART printing timestamps beats guessing. GPIO toggling for timing measurement (the poor man's logic analyzer). When the hardware "doesn't work," the veteran verifies the firmware's assumptions (clock tree configured? peripheral enabled? pin muxed?) before suspecting silicon.
When to call a specialist: RF matching/antenna tuning beyond basic pi-networks (the network-analyzer expert earns their fee in one session); signal-integrity simulation for >1 Gbps interfaces (HyperLynx/SIwave time); failure analysis requiring decapsulation or X-ray (a lab service); functional-safety certification (TÜV/exida — a process, not a person).
Original ETS reference writing, verified against public sources on 2026-09-30. Thin sourcing is flagged inline. Not legal advice — confirm current editions with the issuing body.